Course Description
In this course, you explore high-level design planning and implementation by using the Encounter? Digital Implementation software. You learn several techniques for floorplanning and placement while implementing timing closure strategies. You run the detail router to route a design, fix routing violations, and use timing and signal integrity options.
Other topics in this course include extracting parasitics, creating clock trees, running delay calculation, and using database access commands. You also explore wire editing, metal fill, ECO, and physical verification.
This course was formerly called Floorplanning, Physical Synthesis, Place and Route (Flat).
Learning Objectives
After completing this course, you will be able to:
Floorplan a design
Place blocks and standard cells
Run scan optimization
Run Trial Route and route the power
Estimate parasitics and generate timing information
Analyze routing congestion
Create clock trees
Run power analysis
Modify net attributes
Edit wires manually
Route with signal integrity options
Extract RC data
Optimize and close timing
Fix routing violations
Route in ECO mode
Run database access commands
Run foundation flow scripts
Software Used in This Course
Encounter Digital Implementation System XL
Software Release(s)
EDI111
Course Agenda
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
Unit 1
Floorplanning the design
Planning power
Routing power
Placing cells and blocks
Optimizing and reordering scan chains
Analyzing route feasibility using Trial Route
Unit 2
Extracting parasitics and analyzing timing
Running optimization and closing timing
Implementing the clock tree
Analyzing power
Unit 3
Selecting routing attributes and options
Performing wire editing and metal fill
Running signal integrity
Running database access commands
Implementing an engineering change order
Writing out a design
Creating and running Foundation Flow scripts
首頁 課程表 報名 在線聊 講師 品牌 QQ聊 活動 就業
