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　HSIM是全球第一個滿足深亞微米設計需求的全電路、層次化的晶體管級仿真器。它可以準確的仿真電路的各種行為，包括：電路的功能、電壓和電流波形、時序和功率信息、電源網絡的電壓降、串擾噪聲以及地彈反射等。由于采用了創新的層次化數據存儲和同構匹配算法，HSIM對仿真的電路規模幾乎沒有限制。層次化數據存儲免除了仿真器處理電路臃余單元和子電路對內存的需求，因此HSIM可以容易地做到高容量的全電路仿真；同構匹配可以減少對臃余單元和子電路的計算量。
HSIM為高級IC設計人員提供了一整套全芯片電路驗證所需要的功能，包括：?
·分級存儲：應用高效分級結構數據庫減少內存使用量并擴大電路尺寸。?
·回歸模塊矩陣解算程序：采用分級結構進行電路模擬，精度接近SPICE。?
·分級RC抑制算法：降低分級結構電路數據庫中寄生電阻和電容的復雜程，減少精度損失。?
·布局之后寄生現象的后向注解：提供有效的布局后模擬和分析，存儲器需求少。?
HSIM可以向SPICE一樣用于任何電路的瞬態仿真，而且它比SPICE快無數倍。
HSIM的強項在于它維持高精度和快速的情況下，對數以千萬記的晶體管的仿真能力。
HSIM的用戶可以用它來對大的電路模塊、一組電路模塊或者整個電路做晶體管級仿真。
兩天的課程安排：
第一階段
　　　　 HSIMplus platform overview
　　　　 Software download and installation
　　　　 HSIM input/output files
　　　　 Basic HSIM setup
第二階段
　　　　 Accuracy vs speed
　　　　 Back-annotation
　　　　 Interactive debugging

This training will teach you how to use the Synopsys HSIM FastSpice simulator. It will introduce HSIMplus, a comprehensive platform for simulation and analysis of high performance analog, mixed-signal, memory, and system on-chip designs including important post-layout effects.

The HSIMplus platform is built on the HSIM simulator to provide a fully integrated solution for nanometer IC design, including options for dynamic voltage drop analysis considering the timing impact of power net variation; reliability analysis of power and signal nets; coupling capacitance and dynamic crosstalk behavior; and MOSFET device reliability. Integrations with Cadence’s analog design environment and various HDL simulators, as well as circuit screening complete the set of available options.

 

第二階段

Unit 1 Hsim basic training

?HSIM instruction

?HSIM Technology

?Setting HSIM Parameters

?HSIM Speed/accuracy tradeoff adjustment

?HSIM DC Analysis

?Interactive Debugging

?Misc. Features

Unit 2 Hsim advanced training

?Postlayout Simulation Flow

?Power Net/Signal Net/Mosfet Reliability Analysis

?Co-Simulation instruction

?Customer Support Introduction

 

OBJECTIVES

At the end of this workshop the student should be able to:

• Learn the fundamentals of HSIM
• Learn how to set up a basic simulation
• Learn timing and power analysis commands
• Learn netlist settings for back-annotation
• Acquire hands on experience from course lab exercises

AUDIENCE PROFILE

This training is targeted for analog and/or mixed-signal designers.