久久久影院免费_波多野结衣一区_亚洲国产一区二区在线观看 _日韩中文欧美

        1、培訓過程中，如有部分內(nèi)容理解不透或消化不好，可免費在以后培訓班中重聽；
        2、課程完成后,授課老師留給學員手機和Email,保障培訓效果,免費提供半年的技術(shù)支持。
        3、培訓合格學員可享受免費推薦就業(yè)機會。

培訓方式以講課和實驗穿插進行。

Cadence? Incisive? Enterprise Simulato主要利用系統(tǒng)級至門級的涵蓋率來驅(qū)動功能驗證和除錯分析進一步促進的驗證的效率及可預(yù)測性。Cadence Incisive Enterprise Simulator?提供testbench制作、共用和分析能力，可從系統(tǒng)級至RTL再到門級驗證其設(shè)計，利用此環(huán)境從計劃至完成皆可支援涵蓋范圍驅(qū)動的運算法，而其原位編譯的模組可在傳統(tǒng)同步模擬加速並同時模擬關(guān)于behavior、transation(TLM)?、RTL和門級模型，以達到有效改善同步模擬的不良性能。它也支援工業(yè)標準的驗證語言並且與開放驗證運算法相容(OVM)，因此工程師能迅速簡單地整合Cadence Incisive Enterprise Simulator以建立所需要的驗證流程。

COURSE OUTLINE

MDV (Metric Driven Verification) foundations workshop

·?????????MDV Foundations introduction

–??MDV Foundations Planning

–??Introduction to Planning

·?????????Verification Plan Development

–??Lab 1: Launching Your First Regression

–??Lab 2: Review the Default vPlan View in Enterprise Manager

–??Lab 3: Creating Reusable Verification Plans

–??Lab 4: Creating a Top Level Verification Plan

–??Lab 5: Detecting Changes in the New Specification

–??Lab 6: Review the vPlan in vManager

·?????????MDV Foundations Infrastructure ?

–??Lab 1: Your First Enterprise Manager Regression

–??Lab 2: Integrating project build and run

·?????????MDV Foundations Management

–??Lab 1: Create your own first failures view

–??Lab 2: Rerun Failures

–??Lab 3: vPlan Analysis

–??Lab 4 : Report generation

?

Low Power Verification Workshop

???????????Introduction

–????????Introduction to Low Power Terminology

–????????CPF Creation

–????????Lab: Understanding the power information from a CPF file - Solution

???????????Low Power Simulation Verification

–????????Verification Planning and Metrics for Low Power

–????????Low-Power Simulation

–????????TCL Commands for Debug

–????????Debugging with SimVision

–????????Automatic Assertions

–????????Lab: Low-Power Simulation Debug

Assura Verification

The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.

Learning Objectives
In this course you will:
? o Verify your physical IC design with Assura Verification?
? o Set up and run DRC and LVS?
? o?Locate and display results from DRC and LVS runs?
? o Run verification in various input and run modes

Audience
? o CAD Developers
? o Design Engineers
? o? Layout Designers

Prerequisites
? o Layout design experience
? o Physical verification experience
? o UNIX OS

Course Agenda

Unit 1

? o?Introduction?
? o?Using Assura Verification?
? o?Operational details?
? o?Inputs and outputs?
? o?Interactive debugging environment?
? o?DRC and LVS runs
? o?Running design-rule checks (DRC)?
? o?DRC error debugging techniques?
? o?Error Layer Window?
? o?Setting up DRC run parameters

Unit 2

? o?Running design rule checks (continued)?
? o?Antenna check?
? o?Density check
? o?Running layout versus schematic (LVS) checks?
? o?Understanding and debugging LVS check reports?
? o?Setting up LVS run parameters?
? o?Displaying errors using the graphical user interface?
? o Locating LVS errors

Unit 3

? o Running layout versus schematic checks (continued)?
? o?Debugging LVS with multiple errors?
? o?Using the main debugging tools?
? o?Mismatched nets and mismatched devices?
? o?Shorts locator and opens locator?
? o?Malformed devices?
? o?Pins, parameters, and rewire tools
? o?Unguided debugger lab module?
? o?Running an electrical rules check (ERC)