久久久影院免费_波多野结衣一区_亚洲国产一区二区在线观看 _日韩中文欧美

        1、培訓過程中，如有部分內容理解不透或消化不好，可免費在以后培訓班中重聽；
        2、課程完成后,授課老師留給學員手機和Email,保障培訓效果,免費提供半年的技術支持。
        3、培訓合格學員可享受免費推薦就業機會。

培訓方式以講課和實驗穿插進行。

Overview
This course covers 2 part of digital IC: Design and Verification.
The first part of this course is an introduction of digital IC design. It gives guidelines on how to set up good coding style for RTL design and how to write RTL for design for different level,from module level to SoC level.
The second part of this course is an introduction to the Incisive Plan-to-Closure Methodology (IPCM). IPCM defines how to perform a verificaiton process by going through plan, execute, measure and react process. It also introduces how to perform the process automatically.This 2 day course shows you how to write HDL code from module to SoC level design. It also provides guidance and practice to perform a coverage-driven-verification process automatically.

Objectives?
In this course, you will:
● Learn how to set up coding style for RTL.?
● Apply the coding style to module-level and SoC-level design?
● Learn how to check coding style?
● Learn a typical verification flow of from plan to closure?
● Learn to implemente the verification process automatically

Course Outline

Unit 1
● Module Level RTL design?
● RTL Coding Style and rule check
● System-On-a-Chip Design

Unit 2
● Verification Methodology
● Verification Plan
● Verification Execute
● Verification Measure
● Verification React
● Verification Process Management

Audience Profile

Design Engineers & Verification Engineers
At least one of the SystemC, VHDL, and Verilog languages SystemVerilog Language and Application? Basic digital IC design, simulation, verification knowledge

?

Synopsys Tools Used?
ncisive® DesignTeam Simulator