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嵌入式OS--4G手機操作系統

手機/網絡/動漫游戲開發

嵌入式OS--WinCE

單片機培訓

嵌入式硬件設計

嵌入式OS--VxWorks

PowerPC嵌入式系統/編譯器優化

3G手機軟件測試、硬件測試

云計算、物聯網

開源操作系統Tiny OS開發

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　　培訓班新動態 　

　　Encounter RTL Compiler培訓班

Course Description

In this course, you explore the features of the Cadence? Encounter? RTL Compiler with global synthesis technology. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, optimize for low power, and interface with other tools.

Learning Objectives

After completing this course, you will be able to:

• Apply the recommended global synthesis flow using Encounter RTL Compiler.
• Navigate the design database and manipulate design objects.
• Constrain designs for global synthesis and run static timing analysis.
• Optimize RTL designs for timing and area using several strategies.
• Diagnose and analyze synthesis results.
• Use the extended datapath features of the compiler.
• Analyze and synthesize the design for low-power.
• Interface with other tools and place-and-route flows.

Course Agenda

Note that this course can be tailored to better meet your needs –?contact the Cadence training staff?for specifics.

Unit 1

• About this Course
• Introduction to Encounter RTL Compiler
• HDL Modeling
• Synthesis Flow
• Datapath Synthesis
• Optimization Strategies

Unit 2

• Low-Power Synthesis
• Interface to Other Tools
• Test Synthesis