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OVERVIEW

In this two-day workshop, you will learn how use TetraMAX?--Synopsys' ATPG Tool for SOC design--to perform the following tasks:

• Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
• Describe the test protocol and test pattern timing using STIL
• Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
• Troubleshoot fault coverage problems
• Save and validate test patterns
• Troubleshoot simulation failures

This class includes an overview of the fundamentals of manufacturing test, such as:

• What is manufacturing test?
• Why perform manufacturing test?
• What is a stuck-at fault?
• What is a scan chain?

This class also includes a brief overview of the DSM Test Failure Diagnosis and Adaptive Scan features in TetraMAX?.

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OBJECTIVES

At the end of this workshop the student should be able to:

• Incorporate TetraMAX? ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
• Create a STIL Test Protocol File for a design by using QuickSTIL menus or commands, DFT Compiler or from scratch
• Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
• Customize a Test Protocol for a design that requires special circuit initialization, scan shift or capture procedures or pattern timing
• Describe when and how to use at least four options to increase test coverage and/or decrease the number of required test patterns
• Save test patterns in a proper format for simulation and transfer to an ATE
• Validate test patterns using STIL Direct Pattern Validation

AUDIENCE PROFILE

ASIC, SoC or Test Engineers who perform ATPG at the Chip or SoC level.

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PREREQUISITES

To benefit the most from the material presented in this workshop, students should: Have taken the DFT Compiler 1 workshop or possess equivalent knowledge with DFT Compiler and fundamentals of manufacturing test including:

• Understanding the differences between manufacturing and design verification testing
• Stuck-at fault model
• Internal and boundary scan chains
• Scan shift and capture violations
• Major scan design-for-test rules concerning flip-flops, latches and bi-directional/tri-state drivers
• Tradeoffs between having single or multiple
• Understanding of digital IC logic design
• Working knowledge of Verilog or VHDL language
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

COURSE OUTLINE

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第一階段:

Introduction to ATPG Test

Building ATPG Models

Running DRC

Controlling ATPG

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第二階段:

Minimizing ATPG Patterns

Writing ATPG Patterns

Pattern Validation

Diagnosis

??? Conclusion