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The class begins with how to load the required synthesis and physical data required by IC Compiler (data setup), followed by creating a floorplan, including power grid, to meet timing and routeability throughout the flow (design planning). The placement flow focuses on optimizing the placement and logic for timing, congestion, power, and scan-chain ordering. The CTS unit covers controlling and building clock trees and performing additional timing optimization, followed by routing of the clock nets. In the routing unit, you will learn the signal routing and optimization steps based on the Zroute mode, including concurrent via doubling and antenna fixing. The chip finishing unit includes steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and metal filling.

Every lecture is accompanied by a comprehensive hands-on lab.

課程目標

Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
Perform placement and related optimizations to minimize timing violations, congestion, and power
Analyze congestion maps and timing reports
Perform pre-CTS power optimization
Perform clock tree synthesis
Analyze clock and timing results post-CTS
Route the clock nets
Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
Analyze and fix physical DRC and LVS violations
Perform functional ECOs
Perform chip finishing steps
Generate output files required for final validation/verification

班級規(guī)模及環(huán)境--熱線:4008699035 手機:15921673576/13918613812( 微信同號)

堅持小班授課，為保證培訓效果，增加互動環(huán)節(jié)，每期人數(shù)限3到5人。注意：本課程一旦開課不予退費。

時間地點

上課地點：【上海】：同濟大學(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學成教院【北京分部】：北京中山/福鑫大樓【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路）【成都分部】：領館區(qū)1號（中和大道）【沈陽分部】：沈陽理工大學/六宅臻品【鄭州分部】：鄭州大學/錦華大廈【石家莊分部】：河北科技大學/瑞景大廈【廣州分部】：廣糧大廈【西安分部】：協(xié)同大廈
近開課時間(周末班/連續(xù)班/晚班）：IC Compiler 1班：2025年12月15日..以質(zhì)量求發(fā)展....合作共贏....實用實戰(zhàn)....用心服務..........--即將開課--........................(歡迎您垂詢，視教育質(zhì)量為生命！)

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課程大綱:

IC Compiler 1 培訓

課程內(nèi)容：

階段 1

Introduction and Overview
Data Setup and Basic Flow
Design Planning

階段 2

Design Planning (Lab continued)
Placement
Clock Tree Synthesis

階段 3

Clock Tree Synthesis (Lab continued)
Routing
Chip Finishing
Customer Support

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